This application claims priority from Korean Patent Application No. 2001-23458, filed on Apr. 30, 2001, the contents of which are incorporated herein by this reference in their entirety.
1. Field of the Invention
The present invention relates to a semiconductor device having a trench isolation structure and to a method for fabricating the same.
2. Description of the Related Art
As semiconductor devices become more highly integrated, various approaches have been used to further scaling down the semiconductor devices. Specifically, a cell array area of the semiconductor devices can be reduced by employing a shallow trench isolation structure (STI) instead of a local oxidation of silicon (LOCOS) isolation structure. But, the trench isolation structure is employed, various defects that affect various device characteristics can occur, because a semiconductor substrate is etched to form a trench region. Thus, several processing techniques are introduced to cure such defects generated during the formation of the trench region.
FIGS. 1 through 3 are process cross-sectional views illustrating a semiconductor device having a conventional trench isolation structure. In the drawings, the reference character xe2x80x9caxe2x80x9d corresponds to a cell array region and the reference character xe2x80x9cbxe2x80x9d corresponds to a peripheral circuit region including PMOS transistors.
Referring to FIG. 1, a buffer oxide layer 102 and a hard mask layer 104 are formed on a semiconductor substrate 100. The hard mask layer and the buffer oxide layer are patterned using a photoresist pattern 106 as an etch mask to form the buffer oxide layer pattern 102 and the hard mask pattern 104, which are sequentially stacked.
Referring to FIG. 2, the photoresist pattern 106 is removed, and the semiconductor substrate 100 is etched using the hard mask pattern 104 as an etch mask to form a trench region. The trench region in turn defines an active region. Then, a trench oxide layer 108 is formed on the side walls of the trench region, and a nitride layer 110 is conformally formed on the side wall of the trench oxide layer 108. Continuously, an insulation layer 112 is formed to fill up the region surrounded by the nitride layer 110.
Referring to FIG. 3, the insulation layer 112 is planarized using a chemical mechanical polishing (CMP) process. As a result, a nitride liner 110a is formed on the trench oxide layer 108, and an insulation layer pattern 114 is formed in the region surrounded by the nitride liner 110a. Then, after recessing a top of the insulation layer pattern 114, the hard mask pattern 104 is removed using a wet etch of a phosphoric solution to form a device isolation layer.
As described above, in a conventional technique, trench isolation layers of the cell array region and the peripheral circuit region are formed at the same time. In other words, the thickness of the trench oxide layer in the cell array region is the same as that of the trench oxide layer in the peripheral circuit region. In this case, the thickness of the trench oxide layer directly affects the characteristic of MOS transistors formed in the active region. These problems are further explained through FIGS. 4 and 5.
FIG. 4 is a cross-sectional view illustrating a phenomenon where the device characteristics of the MOS transistor degrade if the thickness of the trench oxide layer is relatively thick.
Specifically, if a trench oxide layer 108a, that is, a trench thermal oxide layer formed on the side wall of the trench region is relatively thick, the top corner of the trench region develops a sharp recess, as shown in FIG. 4. Further, during the removal of the hard mask pattern 104 of FIGS. 1 and 2 and the buffer oxide layer pattern 102 of FIGS. 1 and 2, the trench oxide layer 108a can be over-etched, thereby forming a recessed region 40. A gate oxide layer 32 is formed on the active region of the resulting structure having the recessed region 40, and a gate electrode 34 is formed overlying the gate oxide layer 32 and the device isolation layer.
If recessed regions 40 are formed at the top corners of the trench region, even though a subthreshold voltage, i.e., the lower than a threshold voltage, is applied to the gate electrode 34, a channel can be formed on the top portions of the sidewalls of the trench region due to an inverse narrow-width effect. Here, the subthreshold voltage is. This is because a strong electric field is locally concentrated on the gate oxide layer 32 overlying the sharp top corners of the trench region. Consequently, undesirable leakage currents flow between the source region and the drain region in the MOS transistor. Further, the reliability of the gate oxide layer 32 degrades and a gate leakage currents increase. Specifically, when the inverse narrow-width effect occurs in a cell transistor of a DRAM, a short refresh period is required to increase power consumption.
FIG. 5 is a cross-sectional view illustrating the problem where characteristics of the MOS transistor degrade with a relatively thin trench oxide layer.
As illustrated in FIG. 5, if the trench oxide layer 108b is relatively thin, it is possible to prevent formation of the recessed region 40. Further, the top corner of the trench region can have a round shape. Thus, it is possible to improve the characteristics of the leakage currents resulting from the inverse narrow-width effect. However, the nitride liner 110a that covers the side wall of the trench oxide layer 108b is generally known to have a negative charge. Thus, in the case of a thin trench oxide layer 108b, the positive coupling charge can be induced on the sidewalls of a trench region, thus forming an undesirable P-channel. Consequently, if the trench oxide layer 108b is thin, the leakage current characteristic of the PMOS transistor degrades or malfunction thereof can occur.
Therefore, the present invention provides a semiconductor device having trench oxide layers of each different thickness at the region where an NMOS transistor of a cell array region and a PMOS transistor of a peripheral circuit are formed.
The present invention also provides a method for fabricating a semiconductor device that can form trench oxide layers of each different thickness at the region where an NMOS transistor of a cell array region and a PMOS transistor of a peripheral circuit are formed.
In order to approach the object, the present invention includes the first device isolation layer and the second device isolation layer formed in the first area and the second area of a semiconductor substrate, respectively. The first device isolation layer defines an active region of the first area. Likewise, the second device isolation layer defines another active region in the second area. The first device isolation layer consists of the first trench oxide layer, the first nitride liner and the first insulation layer pattern. Here, the first trench oxide layer is formed on the side walls of the first trench region, and the first nitride liner is formed on the side walls of the first trench oxide layer. The first insulation layer pattern fills the region surrounded by the first nitride liner. The second device isolation layer includes the second trench oxide layer, the second nitride liner and the second insulation layer pattern. Here, the second trench oxide layer is thinner than the first trench oxide layer on the side walls of the second trench region. The second nitride liner is formed on the side walls of the second trench oxide layer. The second insulation layer pattern fills the region surrounded by the second nitride liner.
According to one embodiment of the present invention, the active region between first trench regions corresponds to a peripheral circuit region including PMOS transistors, and the active region between the second trench regions corresponds to a cell array region. The first trench region and the second trench region are formed in the first area and the second area, respectively. Then, a first trench oxide layer is formed on the side walls of the first trench region. The second trench oxide layer is formed on the side walls of the second trench region. The second trench oxide layer is thinner than the first trench oxide layer. Next, the nitride layer is conformally formed on the side walls of the first trench oxide layer and the second trench oxide layer. Then, the first insulation layer pattern is formed in the first trench region to fill the region surrounded by the nitride layer. The second insulation layer pattern is formed in the second trench region to fill the region surrounded by the nitride liner. As a result, the first device isolation layer is formed in the first area, and the second device isolation layer is formed in the second area. Here, the second trench oxide layer is thinner than the first trench oxide layer.
According to another embodiment of the present invention, to form first and second trench oxide layers, a buffer oxide layer and a hard mask layer are sequentially formed on the semiconductor substrate having the first and the second areas. Then, the hard mask layer, the buffer oxide layer and the semiconductor substrate are sequentially patterned to form the first trench region in the first area. The first thermal oxidation process is performed on the resulting structure where the first trench region is formed. Next, the hard mask layer, the buffer oxide layer and the semiconductor substrate are sequentially patterned to form the second trench region in the second area. The second thermal oxidation process is performed on the resulting structure where the second trench region is formed. Thus, the first trench oxide layer is more thickly formed than the second trench oxide layer.
In the semiconductor device according to the present invention, the peripheral circuit including PMOS transistors is formed in the active region between the first trench regions. Also, the cell array region including cell transistors and capacitors is formed in the active region between the second trench regions.